Newsroom

A RISC-V IP and tools specialist Syntacore updates its Linux OS software package with a new boot stack, featuring miniboot, OpenSBI, and U-Boot.

This article provides a comprehensive overview of the SCR1 RISC‑V open-source core, covering its key features, available configurations, software development tools and PPA characteristics.

RISC-V IP provider Syntacore adds support for Zephyr 4.3 in its SCR processor IP.

Syntacore releases an updated all-in-one RISC-V development kit with toolchains, IDEs, debuggers, and simulators.

Syntacore upgrades its SCR3, SCR4, and SCR5 cores with support for Packed-SIMD, Zicond and Zimop extensions.

Learn about the benefits of implementing RISC-V Bit Manipulation and Scalar Cryptography extensions in MCU and APU-class SCR cores.

This article explores the technical features and PPA characteristics of Syntacore’s updated MCU-class SCR1, SCR3, SCR4, and SCR6 cores.

Syntacore upgrades its SCR3, SCR4, and SCR5 cores with support for Bit Manipulation, Scalar Cryptography, and ACLINT/CLIC interrupt controllers.

Syntacore’s Development Toolkit gets an update — all-in-one RISC-V development environment with toolchains, IDEs, debuggers, and simulators.

RISC-V IP and tools specialist Syntacore announces support for Zephyr 4.0 RTOS across its SCR RISC-V processor IP portfolio.

Syntacore’s Development Toolkit receives an update — improved RISC-V development environment with toolchains, IDEs, debuggers, and simulators.

Syntacore Development Toolkit, a ready-to-use RISC-V development platform with pre-configured toolchains, IDEs, debuggers, and simulators, got an update.