Senior DSP Designer/Architect

Required work experience: 3+ years

Responsible for RTL design and development for DSP applications. Works closely with cross-functional teams to deliver high-quality digital designs that meet the stringent requirements of modern DSP systems.

Job Responsibilities:

  • Develop and maintain Verilog RTL logic blocks for communications systems’ baseband
  • Work on test plans with a verification team
  • Develop and maintain architecture (microarchitecture) specifications and other RTL-related documentation
  • Participate in the process of verification, debugging, and coverage improvement
  • Collaborate with a physical design team to ensure compliance with design constraints and timing
  • Work with a power team on power optimization

Requirements:

  • BS or MS degree in CS/EE/CE, or a related field
  • Knowledge of front-end tools (simulation, lint, synthesis, power analysis, formal verification, LEC)
  • Perfect Verilog/System Verilog
  • Experience with version control systems, preferably Git
  • Familiar with Linux operating system
  • Jira, Jenkins
  • Good English (intermediate+)

Good to Have:

  • Experience with wireless communication systems and their development, knowledge of relevant standards
  • Scripting languages (TCL, Python, Shell etc.)

Key Skills:

Verilog, HDL, CPU, DSP, RTL, SystemVerilog, ASIC Microarchitecture

Leadership, communication, planning, management, team work, self-driven

 

Please contact us at hr@syntacore.com if you are interested to apply or have any further questions.