SCR9 Application Core

SCR9 is a high-performance, silicon-proven, Linux-capable 64-bit RISC-V processor core for entry-level server-class applications and personal computing devices. The SCR9 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "V" Vector Operations, "B" Bit Manipulation, and "K" Scalar Cryptography extensions.

The SCR9 platform includes an out-of-order superscalar dual-issue 12-stage pipeline, a high-performance double-issue floating-point unit, PLIC or APLIC units for an advanced interrupt processing, and industry-standard AXI4 and JTAG interfaces increasing flexibility and compatibility. SCR9 includes an enhanced data prefetcher, optimized L1 and L2 caches, and an L3 network-on-chip cache with capacity up to 16MB. A hardware hypervisor, vector operations and heterogeneity support enable the design of multi-cluster architectures capable of running AOSP and Linux operating systems. The SCR9 core can operate in heterogenous multicore (up to 16 cores in a cluster) environments, offering hardware-level support for memory coherency and simplified external accelerators' integration.

SCR9 Application Core


  • High performance computing
  • AI and ML
  • Computer vision
  • Entry-level servers
  • Video Processing
  • PC and Laptops

SCR9 Key Features

ISA RV64GC[V][B][K], Vector Operations [V], Bit Manipulation [B], Scalar Cryptography Instructions [K] — optional
Pipeline Out-of-order 12-stage superscalar
Floating-Point Unit (FPU) Single/Double-precision, IEEE 754-2008 standard
Multicore Support (SMP) Up to 16 cores with cache coherency
Branch Prediction Unit (BPU) Static/Dynamic
Vector Processing Unit (VPU) Vector register length 128-bit
Memory Subsystem
L1 Cache Up to 64KB + 64KB, error protection — parity/ECC
L2 Cache From 128KB to 2MB, error protection — SECDED (ECC)
Shared L3 Cache From 4 to 16MB
Memory Management Unit (MMU) Up to 64 TLB instruction entries, up to 64 TLB data entries. Shared L2 TLB with configurable size up to 2k entries
Physical Memory Protection Unit (PMP) Configurable, up to 32-region PMP
Interrupt Subsystem
Platform-level interrupt controller (PLIC) Up to 1023 interrupt lines, up to 256 priority levels
Advanced Interrupt Architecture (AIA) Advanced platform level interrupt controller (APLIC) + Incoming Message Signaled Interrupt Controller (IMSIC) up to 1023 interrupt lines, up to 2047 distinct interrupt identities at each hart
Debug Subsystem
Interface JTAG-compliant interface
Breakpoints Up to 8 hardware breakpoints, unlimited software breakpoints support
AXI Master AXI4 AMBA standard interface
Slave AXI4 AMBA standard interface
External Ports L3 cache coherency port
Timers and Counters
Performance Monitoring Up to 32 performance counters
Embedded 64-bit RTC Timer Machine-mode timer interrupt support

Development Tools

Syntacore Development Toolkit (SCR9 Optimized)

The SC-DT package is a ready-to-use software development kit containing pre-built and pre-configured tools that simplify software development for the SCR9 core. With SC-DT, you can take advantage of the pre-built tools and configurations to reduce the time and effort required to get up and running with SCR9. SC-DT supports Windows, Linux, and RISC-V Linux operating systems and includes:

  • Eclipse IDE and Visual Studio Code plugin
  • Compilers (GCC, LLVM) with optimized libraries
  • Debuggers (GDB with gdbserver, OCD)
  • Simulator (QEMU)
  • FreeRTOS
  • Native Toolkit (designed to run on the RISC-V SCR Linux host)
  • BSP and HAL
  • Application examples
  • Benchmarks
  • Documentation

Syntacore also supports and maintains system software such as Linux, Zephyr, OpenJDK, and U-boot that are not part of the SC-DT package and are downloadable separately.