SCR7 Application Core
SCR7 is a high-performance, silicon-proven, Linux-capable 64-bit RISC-V processor core optimized for applications that demand powerful data processing capabilities.
The SCR7 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "V" Vector Operations, "B" Bit Manipulation, and "K" Scalar Cryptography extensions. SCR7 includes an out-of-order superscalar dual-issue 12-stage pipeline, a floating-point unit, a branch prediction unit, a vector processing unit, PLIC or APLIC units for an advanced interrupt processing, and industry-standard AXI4 and JTAG interfaces increasing flexibility and compatibility.
The SCR7 memory subsystem includes L1 and L2 caches, an MMU unit with TLB, a PMP unit and provides the execution of Linux-based operating systems. The processor core can operate in heterogenous multicore (up to 8 cores in a cluster) environments, offering hardware-level support for memory coherency and simplified external accelerators' integration.
Applications
- High performance computing
- AI and ML
- Computer vision
- Networking
- Video Processing
- Storage
SCR7 Key Features
| Core | |
|---|---|
| ISA | RV64GC[V][B][K], Vector Operations [V], Bit Manipulation [B], Scalar Cryptography Instructions [K] — optional |
| Pipeline | Out-of-order 12-stage superscalar |
| Floating-Point Unit (FPU) | Single/Double-precision, IEEE 754-2008 standard |
| Multicore Support (SMP) | Up to 8 cores with cache coherency |
| Branch Prediction Unit (BPU) | Static/Dynamic |
| Vector Processing Unit (VPU) | Vector register length 128-bit |
| Memory Subsystem | |
| L1 Cache | Up to 64KB + 64KB, error protection — parity/ECC |
| L2 Cache | From 128KB to 2MB, error protection — SECDED (ECC) |
| Memory Management Unit (MMU) | Up to 64 TLB instruction entries, up to 64 TLB data entries. Shared L2 TLB with configurable size up to 2k entries |
| Physical Memory Protection Unit (PMP) | Configurable, up to 32-region PMP |
| Interrupt Subsystem | |
| Platform-level interrupt controller (PLIC) | Up to 1023 interrupt lines, up to 256 priority levels |
| Advanced Interrupt Architecture (AIA) | Advanced platform level interrupt controller (APLIC) + Incoming Message Signaled Interrupt Controller (IMSIC) up to 1023 interrupt lines, up to 2047 distinct interrupt identities at each hart |
| Debug Subsystem | |
| Interface | JTAG-compliant interface |
| Breakpoints | Up to 8 hardware breakpoints, unlimited software breakpoints support |
| Interfaces | |
| AXI | Master AXI4 AMBA standard interface |
| External Ports | TCM AXI slave port, L2 cache coherency port |
| Timers and Counters | |
| Performance Monitoring | Up to 32 performance counters |
| Embedded 64-bit RTC Timer | Machine-mode timer interrupt support |
Development Tools
Syntacore Development Toolkit (SCR7 Optimized)
The SC-DT package is a ready-to-use software development kit containing pre-built and pre-configured tools that simplify software development for the SCR7 core. With SC-DT, you can take advantage of the pre-built tools and configurations to reduce the time and effort required to get up and running with SCR7. SC-DT supports Windows, Linux, and RISC-V Linux operating systems and includes:
- Eclipse IDE and Visual Studio Code plugin
- Compilers (GCC, LLVM) with optimized libraries
- Debuggers (GDB with gdbserver, OCD)
- Simulator (QEMU)
- FreeRTOS
- Native Toolkit (designed to run on the RISC-V SCR Linux host)
- BSP and HAL
- Application examples
- Benchmarks
- Documentation
Syntacore also supports and maintains system software such as Linux, Zephyr, OpenJDK, and U-boot that are not part of the SC-DT package and are downloadable separately.