Senior RTL verification engineer (DSP)
Required work experience: 6+ years
Job Responsibilities:
- Perform IP functional verification
- Develop an IP regression testing system (in a team)
Requirements:
- Excellent working knowledge of UVM
- 3+ years of hands-on DSP RTL verification/development experience
- Excellent SystemVerilog knowledge
- Knowledge of modern CPU architecture(s)
- Advanced RTL simulator user (any vendor)
- Experience with scripting languages (perl/python/tcl/shell)
- Advanced Linux user
- Written/verbal English for technical communication
Good to have:
- Practical experience with ASM, С
- Experience with continuous integration
- Competency in OVM/UVM, SoC interfaces (AXI, AHB, OCP), cocotb
Key Skills:
SystemVerilog, Verilog, ASIC, SoC, Linux, RTL, Verification
Please contact us at hr@syntacore.com if you are interested to apply or have any further questions.