Technical Lead/Senior RTL Verification Engineer (CPU)

Required work experience: 5–10 years

Job Responsibilities:

  • Develop and review test plans that cover the required CPU IP functionality
  • Develop test environment architecture and tests (including using innovative test generation methods)
  • Review and develop low-level tests in C or Assembler
  • Estimate functionality implementation costs, find compromises based on available resources
  • Review and develop scripts for automated testing
  • Develop software and user documentation
  • Debug and run tests in RTL simulator, compare results with golden reference models, implement and validate design on an FPGA
  • Develop requirements for golden reference models that capture functional needs necessary for verification
  • Track results of regression runs
  • Stay informed about the latest developments and activities within your specific area of involvement in the RISC-V community
  • Be responsible for test results within the designated scope

Requirements:

  • Knowledge of modern CPU architectures (at least one)
  • Knowledge of С/С++, asm; make (cmake), gcc (llvm), gas, ld, gdb, git, conan
  • Advanced Linux user (including cli & shell programming)
  • English (upper intermediate+)
  • Scripting languages (Python/Tcl/Perl(legacy)/shell)
  • Experience with RTL simulators
  • Hands-on experience with golden reference models
  • FPGA debugging experience

We will consider candidates with a solid basic background.

Good to Have:

  • Debugging experience: Linux kernel, drivers, bsp
  • Knowledge of SystemVerilog
  • Solid knowledge of the RISC-V architecture and ISA
  • Knowledge of AXI, CHI interfaces

Key Skills:

C, Assembler, Linux, MCU, Microprocessors, CPU, Processors, Git, RTOS, Embedded Systems, Software Development, Validation, Verification, SystemVerilog, make, cmake, gcc, llvm, gas, ld, gdb, conan, debug, fpga, simulation

Please contact us at hr@syntacore.com if you are interested to apply or have any further questions.