SCR5 — a New Linux-capable Application-class RISC-V IP from Syntacore
Syntacore, a founding member of the RISC-V Foundation and an expert in IP and tools, unveils the new entry-level Linux-capable 32-bit SCR5 processor core, targeting high-performance embedded applications.
Key features:
- Full compatibility with the RISC-V open ISA
- Linux OS support
- Support for RV32IMAFDC ISA
- In-order 7–9 pipeline with branch prediction
- Speed/area optimized hardware multiplier/divider
- Single/double-precision FPU, IEEE 754-2008 compliant
- User, machine, and supervisor privilege modes
- Memory subsystem with a TCM unit, L1/L2 caches with ECC/parity check
- Configurable MPU up to 32 regions
- MMU with virtual memory support
- Interrupt subsystem, featuring the IPIC unit
- AXI4, JTAG interfaces support
- Advanced debug controller with JTAG interface
- Hardware triggers support
- Scalable up to four cores in heterogeneous clusters
The SCR5 is readily available in standard configurations and comes with a comprehensive suite of pre-configured and optimized development tools. SCR5 is aimed at industrial, internet of things (IoT), industrial automation, automotive, smart home, wearable devices, and sensor hub applications.
Please get in touch with our experts for further information.