5-th RISC-V Workshop

Nov 15, 2016

Syntacore participates in the RISC-V workshop, hosted at Google’s Quad campus in Mountain View, California on November 29–30.

Our experts present a technical talk titled “SCRx: Family of the Synthesizable RISC-V Cores”, where we showcase our RISC-V-compatible IP portfolio, ranging from low-power embedded to high-performance cores, and share near-term development plans. We would also like to invite everyone at our stand to learn more about our products and watch an FPGA-based SCR5 demo application.

Please join us at the event.