SCR RISC-V IP Update: Bit Manipulation, Scalar Cryptography Extensions, and ACLINT/CLIC Support
Syntacore, a RISC-V IP and SW tools expert, upgrades its SCR3, SCR4, and SCR5 cores to include support for Bit Manipulation and Scalar Cryptography (Zkn, Zks, Zbk) extensions, as well as ACLINT/CLIC interrupt controllers. The enhancements are fully compliant with the relevant RISC-V specifications:
- RISC-V Bit Manipulation ISA extensions v1.0.0-38
- RISC-V Cryptography Extensions Volume I Scalar & Entropy Source Instructions v1.0.1
- RISC-V Advanced Core Local Interrupt Specification v1.0-rc4
- Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions v0.9
The newly added extensions specifically address demands of embedded applications where performance and security are essential, including the Internet of Things (IoT), smart sensors, networking and storage devices.
The ACLINT and CLIC IRQ controllers provide more flexible and efficient interrupt management, meeting the needs of SoCs in applications with demanding timing requirements.
For commercial inquiries and technical details, please contact our sales/FAE team.