SCR1 RISC-V IP Overview: Key Features, Configurations, Performance Evaluation and Development Tools

2. Overview

SCR1 is a compact, 32-bit, energy-efficient microcontroller-class core. It has an area starting from just 10Kgates and is suitable for a wide range of domains, starting from general-purpose deeply embedded applications to industrial control and monitoring systems. Thanks to its open nature, the core can also be used for educational and academic purposes.

The core is based on a Harvard architecture with separate instruction and data buses, supports the RV32I/EMC instruction set, includes a configurable 2-4 stage in-order pipeline, an IPIC unit supporting up to 16 interrupts, TCM up to 64KB and industry-standard AXI4/AHB-Lite and JTAG/cJTAG* interfaces. SCR1 is fully compatible with the ratified specifications defined by RISC-V International.

*Available upon request

The SCR1 core is developed in SystemVerilog and distributed under the open source SHL license, allowing unrestricted commercial use. The core comes with pre-configured, tested and regularly updated software, detailed documentation, examples, projects and images for the popular FPGAs, allowing to get started right out of the box. Syntacore offers dedicated professional technical support on a commercial basis, ensuring rapid and seamless integration for your projects.

Technical Specifications

The following are the detailed technical specifications of the SCR1 core.

Table 1. Key technical parameters of the SCR1 core.

*Optional extensions are given in parentheses. The letter coding for the extensions is I: Base Integer, E: Reduced Base Integer, M: Integer Multiplication and Division, C: Compressed Instructions.

Available Configurations

The SCR1 is available in three standard configurations — Min, Base and Max — providing a flexible set of features that can be adapted to meet the unique requirements of your specific application.

• The minimum (Min) configuration supports the RV32EC ISA, includes a two-stage pipeline and a TCM. This configuration features 16 general-purpose registers, making it suitable for deeply-embedded applications such as, for example, IoT sensors where minimal footprint is critical.
• The base (Base) configuration supports the RV32IC ISA, includes 32 general-purpose registers, a 3-stage pipeline, a TCM, an IPIC interrupt controller, support for vectored interrupt mode via the MTVEC register, a debug subsystem with a JTAG/cJTAG interface and 2 hardware breakpoints, offering an optimal balance of area efficiency and performance. This makes it suitable for general embedded applications like industrial control systems.
• The maximum (Max) configuration supports the RV32IMC instruction set, includes 32 general-purpose registers, a 4-stage pipeline, a hardware multiply and divide unit, extended debug functions with the JTAG/cJTAG interface (up to 4 hardware breakpoints), an IPIC interrupt controller and vectored interrupt mode via the MTVEC register, making ideal for high-performance embedded systems such as control systems and automotive electronics that demand maximum processing power.

Table 2. Key features and specifications of the SCR1 core configurations.

Performance

The table below includes the basic PPA (performance, power and area) metrics for three SCR1 core configurations — minimum, base and maximum — using the widely adopted 90LP and 28HPC process technologies.

Table 3. SCR1 core performance characteristics.

Dhrystone 2.1, Coremark 1.0 run from TCM; SC-DT 2025.09, LLVM-20-sc *Obest with LTO; **Obest with ground rules
90LP, 9 track, LVT, typical, 1.2V, 25°C;
28HPC+, 12 track, LVT, typical 0.9V, 25°C;

Performance Comparison: SCR1 vs. ARM

The Table 4 below evaluates the performance and operating frequencies of SCR1 in comparison with ARM Cortex-M0 and M3 cores across 28HPC and 90LP process technologies.

Table 4. Key performance characteristics of SCR1 and ARM Cortex-M0, Cortex-M3 сores.

*SCR1 — 90LP, 9 track, LVT, typical, 1.2V, 25°C; Cortex-M0 — 90LP, Arm SC7 RVT SS 1.08V, 125°C;
**SCR1 — 28HPC+, 12 track, LVT, typical 0.9V, 25°C; Cortex-M3 — 28HPM, 12 track, LVT, typical 0.9V, 85°C

SCR1 surpasses the ARM Cortex-M0 in performance, approaching Cortex-M3 levels. It can be further optimized by enabling the SCR1_NO_DEC_STAGE define for Max configuration, which reduces the processor pipeline by one stage, allowing it to reach Coremark scores of about 3,05 per MHz. Additionally, it offers some improvements in area efficiency and power consumption.

Area and Power Efficiency

The Table 5 below provides characteristics for the 90LP process technology.

Table 5. Area and power efficiency of SCR1 and ARM Cortex-M0, Cortex-M3 cores.

*Area — 90LP, 9 track, LVT, typical 1.2V, 25°C @50MHz, core logic only;
Power — 90LP, 9 track, LVT, worst 1.08V, 125°C @50MHz;
**Cortex-M0 — min configuration, 90LP, 7 track, typical 1.2V, 25°C, 125°C;
***Cortex-M3 — min configuration, 90LP, 7 track, RVT, typical 1.2V, 25°С

3. Configuration Options

On top of standard configurations there is number of architectural and microarchitectural features that can be fine-tuned to better meet the requirements of a specific application. In addition, Syntacore provides comprehensive services and support, including architectural and microarchitectural tuning, ISA configuration and compiler optimizations ensuring optimal implementation adapted to specific project requirements.

The following are key configuration options available for adapting SCR1 to diverse application needs (overall design includes more than 40 configurable options).

Table 6. SCR1 configuration options.

4. Complete Development Platform

In addition to the SCR1 core and HW collateral, Syntacore provides a full set of pre-configured and tested tools that significantly boost productivity and simplify the development workflow.

Professional Software Development Suite

Syntacore Development Toolkit (SC-DT) is a comprehensive solution for developers that includes GCC/LLVM-based toolchains, an integrated development environment with support for Visual Studio Code and Eclipse, GDB and openOCD debuggers, a QEMU simulation environment, a bootloader, system software, sample applications, benchmarks and detailed documentation.

In addition, Syntacore provides extensive support for third-party debugging hardware and software from leading vendors: SEGGER, Lauterbach, Ashling, Digilent, Olimex.

Table 7. SC-DT components and supported 3rd party tools.

*Downloaded separately

FPGA SDK

The FPGA SDK is a ready-to-use project that includes an IP core, peripheral modules, standard interfaces, memory and the ability to add custom peripherals for testing on a specific board.

The SDK includes pre-built images, a bootloader, an OS (Zephyr), tests, HAL and BSP, as well as the Eclipse or Visual Studio development environments.

Off-the-shelf projects are available for the most popular FPGA boards*:

• Digilent Arty (Xilinx)
• Digilent Nexys4DDR (Xilinx)
• Altera Arria-V (Intel)
• Terasic DE10-Lite (Intel)

*Boards from other manufacturers can be considered upon request.

All SDKs for these boards are available on the GitHub repository, ready to install and configure and are continually supported by Syntacore.

Documentation

The SCR1 package includes comprehensive documentation:

• User Manual with detailed technical specifications, configuration guidelines and operational instructions
• External Architecture Specification (EAS) Manual, providing an in-depth description of the SCR1 architecture and microarchitecture, including components, ISA and interfaces
• FPGA SDK Guide, offering step-by-step instructions for FPGA setup, image loading and application development tailored to specific boards

5. Summary

This article describes main architectural and microarchitectural features of the open-source SCR1 core, presents its PPA characteristics, compares it with similar ARM cores, describes development tools and provides an overview of the supported FPGA boards.

Fully compliant with the ratified RISC-V specifications and distributed under the open-source SHL license, SCR1 allows unrestricted use in both commercial and academic applications.

SCR1 is available in three default out-of-the-box configurations — Min, Base and Max — and offers flexible options for further fine-tuning. SCR1 can be customized with the help of our professional team to meet your specific requirements, making it suitable for a wide range of domains — from general-purpose embedded and Internet of Things (IoT) to control and monitoring systems.

SCR1 delivers competitive PPA results compared to similar ARM Cortex-M0 and Cortex-M3 IP cores. The core comes with fully pre-configured tools, an FPGA SDK and detailed documentation for a quick start with professional SLA-based support available.