SCR3 Microcontroller Core

High-performance 32-bit MCU core with RV32IMC ISA, privilege modes and MPU

Block diagram

Key features

  • High-performance 32bit microcontroller core with RISC-V ISA
    • RV32IМ[C], optoinal E extension
  • Harvard architecture, separate Instruction and Data memories
  • 32 or 16 32bit integer registers
  • RV32IMC instruction set, optional E extension
    • 47 Integer (32bit) instructions
    • 27 Compact (16 bit) instructions
    • 8 Multiply/Divide instructions
  • AXI4-, AHB- or OCP-compliant external interface (configurable option)
  • Configurable 3 to 5 stages pipeline implementation
  • User- and Machine-mode privilege levels
  • Optional Memory Protection Unit (MPU)
  • Embedded 64bit RTC timer
  • Tightly Coupled Memory (TCM) support
    • 4..1024KB   
  • Optional configurable Integrated Programmable Interrupt Controller (IPIC)
    • Low interrupt latency
    • 8..128 IRQs
  • Optional high-performance or area-optimized MUL/DIV unit
  • Integrated Debug Controller
    • JTAG-compliant interface
    • HW/SW breakpoints support
    • ROM breakpoints support

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