SCR4 Microcontroller Core

32bit RISC-V MCU core with high-performance FPU

Block diagram

Key features

  • Harvard architecture (separate instruction and data buses)
  • RV32IMCF[D] Instruction set
    • 47 Integer (32-bit) instructions
    • 35 Compact (16-bit) instructions
    • 8 Muliply/Divide instructions
    • 26 Floating-point instructions (Single or Double precision)
  • User and Machine privilege modes
  • High-performance IEEE 754-2008 compliant floating-point unit
    • Configurable single or double precision FP unit
    • Register file of 32 floating-point data registers
  • Configurable high-performance or area-optimized multiply/divide unit
  • Configurable 3 to 5 stage pipeline implementation
  • Configurable AXI4, AHB or OCP external memory interface
  • Tightly coupled memory support
    • 4..1024 KB
  • Optional memory protection unit
  • Optional low latency Integrated Programmable Interrupt Controller
    • 8..128 IRQs
  • Embedded 64-bit real time clock
  • Integrated reach-featured debug subsystem
    • JTAG compliant interface
    • HW/SW breakpoints support
    • ROM breakpoints support

 

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