SCR5 efficient application core

Efficient Linux-capable application core with virtual memory, MMU, L1/L2 caches, coherency and SMP support

Block diagram

Key features

  • Efficient mid-range 32bit RISC-V application core
    • RV32IМC[AFD], 64bit option
  • Harvard architecture, separate Instruction and Data memories
  • 32 32bit integer registers
  • RV32IMC instruction set, optional AFD extensions
    • 47 Integer (32bit) instructions
    • 35 Compact (16 bit) instructions
    • 8 Multiply/Divide instructions
    • 26 Floating point instructions (Single- or Double-precision)
    • 11 Atomic instructions
  • SMP configurations support
  • 7 to 9 stages pipeline, 1GHz+ @tsmc28
  • User-, Supervisor- and Machine-mode privilege levels
  • Fully-featured memory subsystem with Linux support
    • Memory Managements Unit (MMU)
    • Page-based virtual memory
    • L1 and L2 caches with coherency
  • High-performance IEEE 754-2008 compliant floating-point unit
    • Configurable single or double precision FP unit
    • 32 floating-point data registers
  • AXI4-, AHB- or OCP-compliant external interface
  • Embedded 64bit RTC timer
  • Configurable Integrated Programmable Interrupt Controller (IPIC)
    • Low interrupt latency
    • 8..128 IRQs
  • High-performance Integer ALU
  • Integrated Debug Controller
    • JTAG-compliant interface
    • Support for ROM breakpoints

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